Loop in 0.13μm CMOS for Wireless Sensor Networks

Some applications of wireless sensor networks (WSN) require long-term deployments and vanishingly-small unit volumes to make them cost effective and unobtrusive. Energyand area-efficient circuits, as well as eliminating offchip components, are critical to meeting these objectives. A conventional WSN node can be fully integrated in CMOS except for the battery, crystal reference, and antenna. Typically, a PLL and a crystal reference are used for RF synchronization and to position the wireless signal in a desired band for FCC compliance. Crystals, however, require custom packaging that currently prohibits scaling to mm sizes. Moreover, an off-chip antenna increases the size of the node and raises the cost. In this paper, a fully integrated 60GHz frequency-locked loop (FLL) in 0.13μm CMOS is presented using an on-chip patch antenna as both the radiator and reference for frequency generation. The proposed technique efficiently integrates the antenna, eliminates the need for a crystal reference, is FCC compliant, and ensures the node transmits at the antenna’s peak efficiency. The substrate beneath the antenna is shielded by an intermediate metal layer ground plane, freeing up space for active circuits and routing beneath the patch. By integrating circuits in CMOS underneath the patch, and stacking the die on e.g. a thin-film battery, a fully integrated WSN node in mm scale is feasible.